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PolarFire FPGA Board Design User Guide
PolarFire FPGA Board Design User Guide
  1. Home
  2. 1 Designing the Board
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  • Introduction
  • 1 Designing the Board
    • 1.1 Power Supplies
    • 1.2 I/O Glitch
    • 1.3 User I/O
    • 1.4 Clocks
    • 1.5 Reset
    • 1.6 DDR
    • 1.7 Device Programming
    • 1.8 Transceiver
    • 1.9 MIPI Hardware Design Guidelines
    • 1.10 AC and DC Coupling
    • 1.11 Brownout Detection
  • 2 Board Design Checklist
  • 3 Appendix: General Layout Design Practices
  • 4 Revision History
  • Microchip FPGA Support
  • Microchip Information

1 Designing the Board

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PolarFire FPGAs are Flash-based FPGAs that support various high-speed memory interfaces such as DDR3/DDR4, lowest power 12.7 Gbps transceiver (XCVR), built-in low-power dual PCIe Gen2, and fabric I/O such as high-speed I/O (HSIO) and general-purpose I/O (GPIO).

Subsequent sections discuss the following topics:

  • Power Supplies
  • User I/O
  • Clocks
  • Reset
  • Device Programming
  • Transceiver
  • AC and DC Coupling
  • Brownout Detection

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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