4 Revision History

Revision	Date	Description
B	07/2024	The following is a summary of changes made in this revision. Updated Power Supplies to include a link to the Microchip Power Estimator (MPE). Updated Reset for DEVRST_N related information. Removed instances of SPI_EN and IO_CFG_INTF pins from Figure 1-6 in the JTAG Programming section as they are not used during JTAG programming. Updated Brownout Detection for a note related to the brownout detection on any PolarFire supply.
A	11/2023	The following is a summary of changes made in this revision. Converted user guide document to Microchip template. Changed the document number to DS50003612 from UG0726. Updated Table 1-12 with the following changes: Replaced “VDDAUX” with “VDD18”. Changed the power-down sequencing requirement from “Power down VDDI before VDD18, VDD, and VDD25 of that bank” to “Power down VDDI before VDD18, VDD, and VDD25”. Added a footnote mentioning that separate power sources must be used when VDDI = 1.8V and VDD18 = 1.8V. Rephrased Reset to mention that DEVRST_N is not mandatory to be used for warm resets. Added information about the calculation of target impedance in Power Supplies. Added a note regarding I/O glitch during JTAG programming in I/O Glitch. Added a new row for IOD in Table 2-1. Removed the following line from XCVR and placed it under Reset in Table 2-1: “There is one IO_CFG_INTF pin available, which can be used as input”.
11.0	—	The following is a summary of changes made in this revision. Updated Clocks to highlight regional clock implications while migrating designs to different device sizes. Updated Figure 1-9. Added link to PPAT in Clocks for preferred clock inputs connectivity to PLLs, DLLs, and global clock network. Added a note about hot socketing exceptions in Hot Socketing (GPIO Only). In Power Supplies, added a note about power sequencing requirement for I/O calibration. Updated I/O Glitch. Updated PolarFire Decoupling Capacitors.
10.0	—	The following is a summary of changes made in this revision. Added more information in new footnotes for VDD and VDDA in Table 1-1. Added footnote in Table 1-2 to Table 1-8 to specify the objective of decoupling capacitors. Updated I/O Glitch and Table 1-11 for power-up and power-down sequencing requirements for mitigating I/O glitch.
9.0	—	The following is a summary of changes made in this revision. Updated the glitch information in I/O Glitch. Updated Figure 1-5 to power VDDI3 (JTAG Bank) required for cold sparing.
8.0	—	The following is a summary of changes made in this revision. Updated the glitch information in I/O Glitch. Added more information on the VDDI and VDDAUX in Power Supplies.
7.0	—	The following is a summary of the changes made in this revision: Added MIPI Hardware Design Guidelines. Added reset guidelines in Reset. Added power-supply decoupling capacitors for the following device packages: MPF200T-FCG484 (0.8 mm). MPF200T-FCSG536 (0.5 mm). MPF200T-FCG325 (0.5 mm). MPF100T-FCG325 (0.5 mm). MPF100T-FCG484 (0.8 mm).
6.0	—	The following is a summary of the changes made in revision 6.0 of this document: Reference Voltage (VREFx) information updated in Power Supplies. Added basic information about Pin Assignment Tables. Updated Power-Supply Decoupling Capacitors—MPF300T - FCG1152/FCG784/FCG484. Added Power-Supply Decoupling Capacitors—MPF500T - FCG1152/FCG784 (1mm), Power-Supply Decoupling Capacitors—MPF200T - FCG784/FCG484 (1mm), and MPF100T - FCG484 (1mm). Added MIPI Hardware Design Guidelines. Added Reset.
5.0	—	The following is a summary of the changes made in revision 5.0 of this document: Details of power supply decoupling capacitors for MPF300-FCG1152, MPF300-FCG484, MPF300-FCG784, MPF300-FCVG484, and MPF300-FCSG536 devices were updated. XCVR_REF and VDD_XCVR_CLK supply pins details were added. For more information, see Power Supplies). Information about VDDIx and VDDAUXx power supplies was updated. For more information, see Unused Power Supply. A note about the power supply constraint of VDDI3 and VDD_XCVR_CLK pins was added. For more information, see Power Supplies. Details of decoupling capacitors in PolarFire devices were added. For more information, see Table 1-9. Additional information about VDDIx, VDDAUXx, and VDD_XCVR_CLK pins was added. For more information, see Unused Power Supply. The design checklist for XCVR pins was updated. For more information, see Table 2-1. Information about VREF was added to core power supply operation details. For more information, see Power Supplies. Information about cold sparing was updated. For more information, see Cold Sparing. JTAG pin details were updated. For more information, see Table 1-15. The SPI master mode programming connectivity diagram was updated. For more information, see Figure 1-7. Information about device reset was updated. For more information, see Reset. DDR3 and DDR4 placement and routing guidelines were removed. These guidelines are available in PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.
4.0	—	Revision 4.0 was published in September 2017. The sections Termination Schemes and PCB Capacitor Placement and Mounting Techniques were removed from this document.
3.0	—	Following is a summary of changes made in this revision. Added Board Design Checklist. Added the Special Pins section in the Introduction chapter. Updated the Power-up sequence for core supplies. For more information, see Power Supplies and Power-Supply Topology. Removed a note related to XCVR_TX and RX signals under the Unused Power Supply section. Updated the VDDI pin name from VDDIx to VDDI3 in the Device Programming section. For more information, see Device Programming.
2.0	—	Following was a summary of changes made in revision 2.0 of this document. Values in the Power-Supply Decoupling Capacitors—MPF300-FCG484 table were updated. Values and parameters were updated in the SPI Master Mode Programming Pins table. For more information, see Table 1-16. Updated Figure 2. For more information, see Figure 1-2.
1.0	—	The first publication of this document.

B

07/2024