16.13.2 DMAnCON0
| Name: | DMAnCON0 |
| Address: | 0x0FC |
DMA Control Register 0
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | SIRQEN | DGO | AIRQEN | XIP | |||||
| Access | R/W | R/W/HC | R/W/HS/HC | R/W/HC | R/HS/HC | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – EN DMA Module Enable
| Value | Description |
|---|---|
| 1 | Enables module |
| 0 | Disables module |
Bit 6 – SIRQEN Start of Transfer Interrupt Request Enable
| Value | Description |
|---|---|
| 1 | Hardware triggers are allowed to start DMA transfers |
| 0 | Hardware triggers are not allowed to start the DMA transfers |
Bit 5 – DGO DMA Transaction
| Value | Description |
|---|---|
| 1 | DMA transaction is in progress |
| 0 | DMA transaction is not in progress |
Bit 2 – AIRQEN Abort of Transfer Interrupt Request Enable
| Value | Description |
|---|---|
| 1 | Hardware triggers are allowed to abort DMA transfers |
| 0 | Hardware triggers are not allowed to abort the DMA transfers |
Bit 0 – XIP Transfer in Progress Status
| Value | Description |
|---|---|
| 1 | The DMA buffer register currently holds contents from a read operation and has not transferred data to the destination |
| 0 | The DMA buffer register is empty or has successfully transferred data to the destination address |