22.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x0D8

Bit 76543210 
  D1S[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxx 

Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection

Table 22-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[26] 0001 1010PWM3S1P2_OUT
[1] 0000 0001CLCIN1PPS[27] 0001 1011NCO1
[2] 0000 0010CLCIN2PPS[28] 0001 1100CMP1_OUT
[3] 0000 0011CLCIN3PPS[29] 0001 1101CMP2_OUT
[4] 0000 0100FOSC[30] 0001 1110ZCD
[5] 0000 0101HFINTOSC(1)[31] 0001 1111IOC
[6] 0000 0110LFINTOSC(1)[32] 0010 0000DSM1
[7] 0000 0111MFINTOSC(1)[33] 0010 0001HLVD_OUT
[8] 0000 1000MFINTOSC (32 kHz)(1)[34] 0010 0010CLC1
[9] 0000 1001SFINTOSC (1 MHz)(1)[35] 0010 0011CLC2
[10] 0000 1010SOSC(1)[36] 0010 0100CLC3
[11] 0000 1011EXTOSC(1)[37] 0010 0101CLC4
[12] 0000 1100ADCRC(1)[38] 0010 0110U1TX
[13] 0000 1101CLKR[39] 0010 0111U2TX
[14] 0000 1110TMR0[40] 0010 1000U3TX
[15] 0000 1111TMR1[41] 0010 1001SPI1_SDO
[16] 0001 0000TMR2[42] 0010 1010SPI1_SCK
[17] 0001 0001TMR3[43] 0010 1011SPI1_SS
[18] 0001 0010TMR4[44] 0010 1100SPI2_SDO
[19] 0001 0011SMT1[45] 0010 1101SPI2_SCK
[20] 0001 0100CCP1[46] 0010 1110SPI2_SS
[21] 0001 0101PWM1S1P1_OUT[47] 0010 1111I2C_SCL
[22] 0001 0110PWM1S1P2_OUT[48] 0011 0000I2C_SDA
[23] 0001 0111PWM2S1P1_OUT[49] 0011 0001CWG1A
[24] 0001 1000PWM2S1P2_OUT[50] 0011 0010CWG1B
[25] 0001 1001PWM3S1P1_OUT[51] 0011 0011-
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxxx
All Other Resets = uuuuuuu