25.13.4 TxGATE

Timer Gate Source Selection Register

Name:	TxGATE
Address:	0x316,0x327


Bit	7	6	5	4	3	2	1	0
				GSS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – GSS[4:0] Timer Gate Source Selection

Table 25-5. Timer Gate Sources
GSS	Gate Source
GSS	Timer1	Timer3
`11111 - 10110`	Reserved
`10101`	CLC4_OUT
`10100`	CLC3_OUT
`10011`	CLC2_OUT
`10010`	CLC1_OUT
`10001`	ZCD_OUT
`10000`	CMP2_OUT
`01111`	CMP1_OUT
`01110`	NCO1_OUT
`01101`	PWM3S1P2_OUT
`01100`	PWM3S1P1_OUT
`01011`	PWM2S1P2_OUT
`01010`	PWM2S1P1_OUT
`01001`	PWM1S1P2_OUT
`01000`	PWM1S1P1_OUT
`00111`	CCP1_OUT
`00110`	SMT1_OUT
`00101`	TMR4_Postscaler_OUT
`00100`	TMR3_OUT	Reserved
`00011`	TMR2_Postscaler_OUT
`00010`	Reserved	TMR1_OUT
`00001`	TMR0_OUT
`00000`	Pin selected by T1GPPS	Pin selected by T3GPPS