37.1 Rev.B - 12/2021

Section	Changes
Document	Package top markings added Editorial updates throughout the document
PORT	Slew Rate Limit Enable (SLR) bit in the Port Control (PORTCTRL) register added
ADC	PGA initialization time is 20 µs
USART	Description of IrDA Event Input Enable (IREI) bit in Event Control (EVCTRL) corrected
INTCTRL	Added information: When configuring the entire Flash as BOOT section, the IVSEL bit in the CTRLA register is ignored.
TWI	CTRLA.SDASETUP is used in client mode to select the clock hold time to ensure minimum setup time
Electrical Characteristics	Table 33-5: Typical values altered and min./max. values added Table 33-6: Completed Table 33-7: ADC updated Table 33-12: Note added Table 33-13: Note added Table 33-22: Symbol column updated Table 33-23: Value set reduced and updated ADC Table 33-26: values updated ADC Table 33-27: Values updated ADC Table 33-28: Values updated TEMPSENSE Table 33-29: Accuracy value updated AC: Typical values altered and min./max. values added in all tables

Document

PORT

Slew Rate Limit Enable (SLR) bit in the Port Control (PORTCTRL) register added

ADC

PGA initialization time is 20 µs

USART

Description of IrDA Event Input Enable (IREI) bit in Event Control (EVCTRL) corrected

INTCTRL

Added information: When configuring the entire Flash as BOOT section, the IVSEL bit in the CTRLA register is ignored.

TWI

CTRLA.SDASETUP is used in client mode to select the clock hold time to ensure minimum setup time

Electrical Characteristics

ATtiny3224/3226/3227