2.4 Clock Aliasing
One issue that can occur during debugging is to have the logic analyzer sampling rate
set. At a minimum, the sampling rate of the logic analyzer needs to be twice the signal
frequency, with larger integer multiples being better. If set too low, the logic
analyzer will show an alias of the actual frequency rather than the frequency on the
bus.
Tip: Waveforms may appear distorted or uneven
in the logic analyzer, even if the sample rate is at or above twice the input
frequency, which occurs when the instrument gets only a few points on the waveform
every cycle and extrapolates to fill in the gaps.