References

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For information about PCIESS, see PolarFire Family PCI Express User Guide.
For information about regional clock resources and connectivity of the transceivers to the global clock network, see PolarFire Family Clocking Resources User Guide.
For information about available I/O standards, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.
For information about Optimized DFE feature, see PolarFire FPGA SmartDebug User Guide.
For information about implementing transceiver designs on printed circuit boards, see respective UG0726: PolarFire FPGA Board Design User Guide, RT PolarFire FPGA Board Design User Guide, or PolarFire SoC FPGA Board Design Guidelines User Guide.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.