1 Functional Description
(Ask a Question)The transceiver (Figure 1) is divided into four distinct transmit (Tx) and receive (Rx) blocks:
- PMA
- PCS interface block, including a dedicated PCIe PCS
- Transmit PLL (Tx PLL)
- Reference clock inputs
The high-speed PMA blocks connect to the FPGA fabric through the PCS block. The PMA generates the required clocks and converts the transmit data from parallel to serial, and receive data from serial to parallel. Each PMA block includes a connection to a PCS block and associated interface to the FPGA fabric making up a transceiver lane. The PCS interface block provides several industry-standard interfaces for use in protocol-specific designs.
A group of four transceiver lanes is called a quad. Each quad has a local transmit PLL used exclusively within the four transceiver lanes. Additional transmit PLLs are shared between quads.
In addition to the 8b10b, 64b6xb, PIPE, and PMA only blocks, two PCIe PCS logic blocks are included in each device. These blocks include hard embedded logic that provides full-featured PCIe endpoint/root port sub-system. These PCIe sub-systems (PCIESS) have hard connections to multiple transceiver lanes, providing flexibility for ×1, ×2, and ×4 width links. See PolarFire Family PCI Express User Guide for additional information pertaining to PCIe.