3 Signal Integrity Conditioning

The transceivers have many tuning adjustments for the analog portions of the PMA allowing for signal integrity optimizations to the system. These features include Rx Continuous Time Line Equalization (CTLE), Rx termination, polarity inversion, Pre- and Post-cursor output emphasis, output impedance settings, and Tx amplitude adjustment. Transceivers are programmed at startup from default configuration information known to the Libero SoC software based on protocol and data rate specifics supplied by the user during design customization and generation. The Libero configurators generate the Rx and Tx default settings that initialize the transceivers at power on or device reset by toggling the DEVRSTN pin.

Other embedded transceiver features include Decision Feedback Equalization (DFE) within the receiver PMA that further corrects signal imperfections caused by PCB losses and quality of the signal being driven to the Rx. The Rx path also includes an input signal eye monitoring feature.

The user can also control the transceiver settings after device programming using the FlashPro programming cable and the SmartDebug Transceiver software utility. Transceivers have a memory mapped Dynamic Reconfiguration Interface (DRI) allowing SmartDebug to communicate with the transceiver blocks to change and monitor the transceivers in real-time. This feature provides debugging capabilities and altering of the transceivers for optimized performance in the system. After the final SmartDebug signal integrity optimization, the user can export the tuned information back into the Libero SoC software for future design regeneration.

Building a transceiver based design using Libero SoC software flow allows flexibility to improve the transceiver performance within the system. The Libero SoC software sets initial good defaults for the user's custom design based on input information to the transceiver configurators. The user can change the associated transceiver input and output settings using the IO Editor after initial design generation. The user can further enhance the signal integrity qualities of the transceiver after design place, route, and bitstream generation by using the SmartDebug capabilities. This allows user to continue the signal integrity tuning after programming the device in the system and provides a feedback path to include the customized signal integrity settings in subsequent design regeneration.

Both the Signal Integrity views of the IO Editor and SmartDebug Transceiver present the same signal integrity settings for both the transmitter and receiver. The available settings are predefined by the factory providing a flexible means to adjust the XCVR.