7 Revision History

• Added a note related to the CDR lock mode option Lock to Data with 2X Gain in CDR Options.
• Updated the default setting of the Enable Disparity option to "Disabled" for 64b67b in Table 2-7.
• Added a note in Table 2-7 of Transceiver Interface Configurator section to describe that all the options, under 64b6xb Gear Box in the Transceiver Interface PCS Settings can be independently enabled or disabled for 64b66b and 64b67b.

• Updated the supported PCS modes for Tx and Rx (Independent) in Table 2-9 of Half-Duplex Mode.
• Added information related to eye monitor, see Eye Monitoring.
• Updated the information related to SmartDebug Eye Monitor feature in SmartDebug Eye Monitor Utility.

• Added a sentence that the recovered clock is derived from the reference clock and not from the incoming data in the Simulation section.
• Updated PCIE_RATE[1:0] to 1-bit signal from 2-bit and also updated the description, see PCIE_RATE.

• Updated the port name from "LANE#_CLK_REF" to "LANE#_REF_CLK" in Table 1-6, Table 1-10, Table 1-11, Table 1-12, and Half-Duplex Mode.
• Updated the LANE#_RX_VAL clock type to Synchronous in Table 1-6.
• Added a note on how to provide the clock source to LANE#_REF_CLK and the accuracy requirement of the source clock with respect to LANE#_RX_CLK_R. See Table 1-6, Table 1-10, Table 1-11, and Table 1-12.
• Added fourth note under Table 1-24.
• Updated the title of Figure 1-54 to include “MPF200T/MPF300T/MPFS095/MPFS160T/MPFS250T-FCSG536”.
• Added a paragraph in JTAG Support to state that the transceiver I/O implementation is fully compliant with AC-JTAG standard (IEEE1149.6).
• Added a footnote recommending 32-bit PMA latency to clarify 64b66b latency requirements in Table 1-15.
• Removed the “Total Latency (UI)” column from Table 1-15.
• Added 64b66b Latency Considerations.

• Added information about reference clock interface for each die. See Reference Clock Input Pins.
• Changed the PCS_ARSTN signal name to PMA_ARSTN. See PMA and PCS Resets.

• Updated the document title to “PolarFire Family Transceiver User Guide”. Added support for RT PolarFire throughout the document.
• Added a note about ERM logic during lock-to-reference mode. See Enhanced Receiver Management.
• Added Interface Latency.
• Updated Transmit Lane Alignment.
• Added Broadcasting REFCLK to the FPGA Fabric.
• Added JTAG Support.

• Updated information about SATA support. See Table   2.
• Updated information about usage of lower data rates in ERM. See Enhanced Receiver Management.
• Updated Tx lane alignment. See Transmit Lane Alignment.
• Updated information about clock uncertainty. See Timing Constraints.

This user guide was created by merging the following documents:

• UG0677: PolarFire FPGA Transceiver User Guide
• UG0915: PolarFire SoC FPGA Transceiver User Guide

The revision history tables of both the user guides are retained here for the future reference. For information, see Table   2 and Table   3.

• Information about incremental DFE calibration was added. See DFE Calibration.
• Information about Enhanced Receiver Management was updated.
• Information about Transceiver Reference Clock Interface was updated.
• Information about spread spectrum was updated. See Table 28.
• Information about PIPE Port List and PMA Port List was updated.
• Information about Loss of Signal Detect (LOS) was added.
• Information about PMA and PCS Resets was updated.
• Information about Transceiver Reference Clock Configurator was updated.
• Information about Dynamic Reconfiguration Interface was updated.
• Information about Jitter Attenuator was updated.
• Information about Transceiver Initialization was updated.
• Information about Libero Generated Files was updated.

• Information about 8b10b Data Path Interface, 8b10b Bit and Octet Sequencing, and 8b10b System Registers was added.
• Information about 64b6xb Data Path Interface, 64b6xb System Registers, 64b66b Receiver, 64b66b Transmit, 64b67b Transmit, and 64b67b Receive was added.
• Information about None_DFE (Static DFE) was updated. See Enhanced Receiver Management.
• Information about LANE#_CLK_REF port name was added. See Table 7, Table 11, Table 12, and Table 13.
• Information about Table 21 was updated.
• Information about DFE Coefficients was added.
• Information about AC/DC Coupled Connection was updated.
• Information about Table 39 was updated.
• Information about Design for Protocols and Unused Transceiver Pins was updated.
• Information about Half-Duplex Mode was updated.
• Information about Receive Input Buffer was updated.

• Information about physical constraint instances was updated. See Table 34.
• Information about TX and RX interface clock was updated. See Table 16.
• Information about Enhanced Receiver Management was updated.

• Information about capability to support switching between two TXPLLs or two CDR REFCLKs through the DRI interface was added. See Transceiver Interface Configurator.
• Information about LiteFast was updated. See Table 1.
• Information about PCS/FPGA Fabric Interface was added.
• Information about new latency was updated. See Table 15.
• Information about Transceiver Data Path Latency was added.
• Information about footnote was updated. See Table 21.
• Information about PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI was added.
• Information about MPF500 Transceiver and Transmit PLL Layout was updated. See Figure 53.
• Information about JA PLL settings for each preset was added. See Jitter Attenuator.
• Information about Transceiver Modes was added.
• Information about PMA and PCS Resets was updated.
• Information about Custom Protocol Settings was added.
• Information about Table 7, Table 11, Table 12, and Table 13 was updated.

• Information about SATA sub-mode was removed from PIPE.
• Information about RX_IDLE was updated. See Table 7, Table 11, and Table 13.
• Information about LANE#_TX_WCLK input pin was added. See PCS/FPGA Fabric Interface.
• Information about Transceiver Clock Regions was added.
• Information about Reference Clock Disruptions was added.
• Information about Jitter Attenuator was added.
• Information about REFCLK input pins were updated. See Reference Clock Input Pins.
• Information about PMA and PCS Resets was added.
• Information about the interface clocks for the Transceiver PLL was updated. See Table 32.
• Information about Enhanced Receiver Management was added.
• Information about PIPE Interface Compliance Exceptions was added.

• Updated the document for Libero® SoC PolarFire v2.3 release.
• Added information about burst mode receiver, see CDR Options.
• Added information about the alignment of transmit lanes, see Transmit Lane Alignment.
• Added information about Tx loss insertion, see Tx Insertion Loss.
• Added a footnote under Table 34 that describes how to disable the ODT value for the differential REFCLK.
• Added a footnote under Table 32 that describes the minimum pulse width for the PMA reset signal.

• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, 64b66b/64b67b, and PMA Only.
• Information about signal integrity was added. See Signal Integrity Conditioning.
• Information about Bit-slip was updated. See Bit Slip. 8b10b does not support bit slip mechanism.

• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, 64b66b/64b67b, and PMA Only.
• Information about Word Alignment was added as sub-section to 8b10b. See Word Alignment (Byte Boundary or Comma Detect).
• Updated Figure 52 and Figure 53.
• Information about LANE#_RX_VAL port name description was updated. See Table 4, Table 7, and Table 11.

• Information about incremental DFE calibration was added. See DFE Calibration.
• Information about Enhanced Receiver Management was updated.
• Information about Transceiver Reference Clock Interface was updated.
• Information about spread spectrum was updated. See Table 28.
• Information about PIPE Port List and PMA Port List was updated.
• Information about Loss of Signal Detect (LOS) was added.
• Information about PMA and PCS Resets was updated.
• Information about Transceiver Reference Clock Configurator was updated.
• Information about Dynamic Reconfiguration Interface was updated.
• Information about Jitter Attenuator was updated.
• Information about Transceiver Initialization was updated.
• Information about Libero Generated Files was updated.

• Information about 8b10b Data Path Interface, 8b10b Bit and Octet Sequencing, and 8b10b System Registers was added.
• Information about 64b6xb Data Path Interface, 64b6xb System Registers, 64b66b Receiver, 64b66b Transmit, 64b67b Transmit, and 64b67b Receive was added.
• Information about None_DFE (Static DFE) was updated. See Enhanced Receiver Management.
• Information about LANE#_CLK_REF port name was added. See Table 7, Table 11, Table 12, and Table 13.
• Information about Table 21 was updated.
• Information about DFE Coefficients was added.
• Information about AC/DC Coupled Connection was updated.
• Information about Table 39 was updated.
• Information about Design for Protocols and Unused Transceiver Pins was updated.
• Information about Half-Duplex Mode was updated.
• Information about Receive Input Buffer was updated.