v2024.2

1 What's New
Information about what is new in Libero SoC Design Suite
2 Download Help
Information to help you download the Libero SoC Design Suite documentation
3 SmartHLS Compiler
Information about SmartHLS Compiler
4 Installation and Licensing
Information about Libero SoC software installation and licensing
5 Design Flow
Information about Design Flow
6 Block Flow
Information about Block Flow
7 SmartDesign
Information about SmartDesign
8 Netlist Viewer
Information about Netlist Viewer
9 I/O Editor
Information about I/O Editor
10 PDC Commands
Information about PDC commands for all families
11 Chip Planner
Information about Chip Planner
12 Timing Constraints Editor
Information about Timing Constraints Editor
13 SmartTime Static Timing Analyzer
Information about SmartTime Static Timing Analyzer
14 SmartPower
Information about SmartPower
15 Programming and Debugging
Information about Programming and Debugging
16 Macro Library
Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire
17 Custom Flow
Information about Custom Flow
18 Design Separation Methodology
Information about Design Separation Methodology
19 Microchip Separation Verification Tool
Information about Microchip Separation Verification Tool
20 PolarFire SoC Microcontroller Subsystem (MSS)
Information about PolarFire SoC Microcontroller Subsystem (MSS)
21 Tcl Command Reference
Information about Tcl Command Reference
22 Additional Information
Additional information about other Microchip products
23 Technical Support
24 About Microchip
More information about Microchip

6.4.4.1 Floorplanning with PDC Commands

You can use the define_region PDC command to create a rectangular or rectilinear region, and then use the assign_region PDC command to constrain all the macros to that region.

Floorplanning reduces the risk of placement conflicts of the blocks at the top level. If you do not constrain your block placement, its components may be placed anywhere on the die.

It is also important to consider the placement of all Block Interface Instances at the boundaries of block regions. This facilitates the interconnection of the block to the top-level design. If the block is highly optimized (densely packed), there may be no routing channels available to connect to any internal Block Interface Instances. Placing all interfaces at block boundaries helps you eliminate routing congestion and failure.