2.2 ICSP Mode Entry

ICSP mode is entered by a specific sequence on the MCLR, PGECx and PGEDx pins. PGECx/PGEDx may be selected from the three available pairs (PGEC1/PGED1, PGEC2/PGED2 or PGEC3/PGED3).

To enter ICSP mode, the following steps must be taken:

  1. Power the device. VDD should remain stable throughout all ICSP operations. Cycling power is not required, so the external programming tool and target chip or circuit may be independently powered; however, a shared VSS ground reference is required.
  2. Drive MCLR low.
  3. Begin driving PGECx and PGEDx low. PGEDx is a “don't care” at this stage, but to simplify subsequent operations, it should be made an output and driven low.
  4. Wait at least 1 ms (no maximum duration).
  5. Pulse MCLR high, then low. Pulse duration must be at least 20 ns, but should be as short as possible. Long durations allow existing code in the target device’s Flash to begin execution. If this user code has RTSP (Run-Time Self-Programming) procedures, then they may modify the Flash memory content. In this case, some programmer steps, such as a verification of the programmed Flash data, may fail. Therefore, do not exceed a MCLR high duration of >2 µs unless unavoidable, and even then, try to minimize the dwell time with MCLR high.
  6. Generate 32 PGECx clock pulses and simultaneously shift the value, 0x8A12C2B2, onto the PGEDx pin, Least Significant bit first. On the wire, if decoded as big-endian octets, this will generate the byte sequence: 0x4D, 0x43, 0x48, 0x51.
  7. After the 32nd falling PGECx clock edge, raise MCLR. The ICSP signal waveforms are shown in Figure 2-10.
    Figure 2-10. ICSP™ Entry Sequence Waveforms (PGECx Pulses from 1 to 32)
  8. Wait at least 500 µs. During this interval, PGECx must remain low, but PGEDx is a don’t care.
  9. Generate 34 PGECx clock pulses to initialize internal clock selection logic. PGEDx for these 34 clocks should be the bit pattern, ‘00’, followed by the 32-bit constant, 0x00801000. The ICSP signal waveforms for this step are shown in Figure 2-11.
    Figure 2-11. ICSP™ Entry Sequence Waveforms (PGECx Pulses from 33 to 66)
  10. Generate 34 PGECx clock pulses to set the (not meaningful) CPU Reset vector target. PGEDx for these 34 clocks should be the bit pattern, ‘00’, followed by the 32-bit constant, 0x00801000 (same as in Step 9). The ICSP signal waveforms for this step are shown in Figure 2-12.
    Figure 2-12. ICSP™ Entry Sequence Waveforms (PGECx Pulses from 67 to 100)

The programmer should continue to hold MCLR high for all subsequent ICSP operations. ICSP mode will terminate when MCLR is pulled low for 1 ms or longer, or VDD is removed.