2.4 ICSP Commands
The ICSP command codes notify the target device what the next operation will be. The codes are followed by a sequence of clocks to shift data into/out of the target. Before issuing any command, the device must first be placed in ICSP mode (refer to the ICSP Mode Entry chapter).
The command codes are a fixed length of two bits, require two PGECx clocks to transfer and are implemented according to Table 2-4 below.
| Binary Command | Mnemonic | Operation |
|---|---|---|
00 | CMDEXEC | Shifts one 32-bit instruction, two 16-bit instructions or half of a 64-bit instruction into the CPU. The instruction(s) are then executed by the target while receiving the next command and its data. |
01 | CMDRD | Sets the PGEDx pin as an output, shifts 32 bits of data from the VISI register onto the pin, then restores PGEDx as an input for the next command. |
10 | CMDSEQWR | Sequentially loads 32 bits of data into memory pointed to by W0
on the target, then post-increments W0 by 4. This command internally
decomposes the 32 bits of PGEDx shift data into a 64-bit
MOV.L instruction executed by the target
processor:
|
11 | CMDSEQRD | Returns the VISI register and internally executes the following
instruction:
When W0 is initialized to a source memory address and W8 contains the address of the VISI register, this command permits sequential memory addresses to be read from the target with minimal overhead. |
The 2-bit command code and 32 bits of data transferred into or out from the target are always presented on the wire, Least Significant bit first.
All command code and data bits, driven onto the PGEDx pin by the programmer, are latched by the target on the rising edge of the PGECx clock. Therefore, the PGEDx state must be valid and stable for at least one setup time before the PGECx rising edge (TDsetup) and held in the same state for at least one hold time after PGECx has risen (TDhold).
When reading data from the target, each of the 32 data bits are outputted/changed on PGEDx by the target on the falling edge of the PGECx clock (still generated by the programmer). The data remain unchanged until the next falling edge, so the programmer should sample the data on or after the rising clock edge, but before it generates another PGECx falling edge.