1 Flash Memory

The Flash memory on dsPIC33AK512MC510 and dsPIC33AK512MPS512 family devices is divided into quadwords (16 bytes each), write rows (512 bytes each) and erase pages (4096 bytes each). The quadword (four 32-bit long words) is the minimum data size which can be written into the Flash. The address of each quadword is aligned by 16 bytes. Also, the Flash memory can be written by rows. Each row consists of 32 quadwords or 512 bytes. The address of each row is aligned by 512-byte boundaries.

The Flash must be erased before a write operation can be initiated. The Flash can be erased by pages. Each erase page consists of eight rows or 4096 bytes. The address of each erase page is aligned by 4096-byte boundaries.

The dsPIC33AK512MC510 and dsPIC33AK512MPS512 family devices’ Flash memory regions are shown in Table 1-1.

Table 1-1. Flash Memory Map
Memory Region			Address	Number of Quadwords	Number of Write Rows	Number of Erase Pages
User OTP			0x7F2C00-0x7F2FFC	64	2	Not applicable
User Configuration A1 (UCA1)			0x7F3000-0x7F3FFC	256	8	1
User Configuration B (UCB)			0x7F4000-0x7F4FFC	256	8	1
User Configuration A2 (UCA2)			0x7FB000-0x7FBFFC	256	8	1
Code Memory	256-Kbyte Flash Memory Devices	Single Boot	800000-83FFFC	16,384	512	64
		Dual Boot	800000-81FFFC	8,182	256	32
		Dual Boot	C00000-C1FFFC	8,182	256	32
	512-Kbyte Flash Memory Devices	Single Boot	800000-87FFFC	32,768	1024	128
		Dual Boot	800000-83FFFC	16,384	512	64
		Dual Boot	C00000-C3FFFC	16,384	512	64

Some dsPIC33AK512MC510 and dsPIC33AK512MPS512 family device registers are used in the programming procedures. These registers’ addresses and descriptions are listed in Table 1-2.

Table 1-2. Registers Used in the Programming Procedures
Register Name	Address	Description
VISI	0x0007C0	This register moves (shifts) data out of the device through the ICSP™ interface.
NVMCON	0x003000	This register selects type and initiates an erase or write Flash operation.
NVMADR	0x003004	The destination Flash address for erase or write operations.
NVMDATA0	0x003008	This register with data is programmed to Flash when quadword write is used.
NVMDATA1	0x00300C	This register with data is programmed to Flash when quadword write is used.
NVMDATA2	0x003010	This register with data is programmed to Flash when quadword write is used.
NVMDATA3	0x003014	This register with data is programmed to Flash when quadword write is used.
NVMSRCADR	0x003018	This register should be set to the address of the RAM buffer loaded with the Flash row data to be programmed.
NVMCRCCON	0x003048	This register controls the Cyclic Redundancy Check (CRC) calculation of the Flash region.
NVMCRCST	0x00304C	This register contains the start address of the 4-Kbyte Flash memory block for the CRC calculation.
NVMCRCEND	0x003050	This register contains the end address of the 4-Kbyte Flash memory block minus one byte for the CRC calculation.
NVMCRCSEED	0x003054	The initial CRC value (seed) should be loaded into this register. If the CRC-32 is calculated for the multiple memory blocks, then the previous CRC result must be written directly to NVMCRCSEED before the next block of CRC calculations.
NVMCRCDATA	0x003058	This register contains the CRC calculation result.