1.1 ROM Code Boot Flow

For Microchip 32-bit MPU devices that embed OTP memory, the ROM code boot flow is shown below.

Figure 1-1. ROM Code Boot Flow
The following sequence is executed out of reset:
  1. JTAG access is kept disabled for the entire ROM code boot sequence.
  2. OTP memory integrity is checked, and the device is locked in case of failure.
  3. CPU and system clocks are configured with a downgraded clock scheme (400/100 MHz for a SAM9X60 device, for example).
  4. The ROM code console is initialized and the “ROMBoot” message is printed to the console.
  5. The NVM interfaces are initialized in the order they are listed in the boot sequence, and the boot code pattern is checked in the first 28 bits read from the NVM.
  6. If the boot code pattern does not match, the entire internal SRAM0 is mirrored at address 0x00000000, over the internal ROM memory. JTAG access is enabled, the USB device is initialized (if an external oscillator is present) and the ROM code switches to the standard monitor, listening for commands from the host.