2.5.1.4.8 Hardware and Software Constraints
The table below provides clock frequencies configured by the ROM code during boot.
| Clock | Frequency |
|---|---|
| PLLA | 396 MHz |
| CPU_CLK | 396 MHz |
| MCK | 99 MHz |
| SDMMC (init/operational) | 400 kHz / 25 MHz |
| SPI | 11 MHz |
| QSPI | 33 MHz |
The NVM drivers use several PIOs in Peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The connected devices could be unintentionally driven at boot time, and thus electrical conflicts between the output pins used by the NVM drivers and the connected devices could occur.
The following table contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. The drive strength of PULL-UP I/O pins is set to High while the pins are used in Peripheral mode by the ROM code.
Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.
| NVM Bootloader | Peripheral | IO Set | Signal | PIO Line | Pull-up |
|---|---|---|---|---|---|
| SD Card/e.MMC | SDMMC_0 | 1 | SDMMC0_DAT0 | PIO_PA15A | X |
| SDMMC0_CMD | PIO_PA16A | X | |||
| SDMMC0_CK | PIO_PA17A | – | |||
| SDMMC0_DAT1 | PIO_PA18A | X | |||
| SDMMC0_DAT2 | PIO_PA19A | X | |||
| SDMMC0_DAT3 | PIO_PA20A | X | |||
| SDMMC_1 | 1 | SDMMC1_DAT1 | PIO_PA2B | X | |
| SDMMC1_DAT2 | PIO_PA3B | X | |||
| SDMMC1_DAT3 | PIO_PA4B | X | |||
| SDMMC1_DAT0 | PIO_PA11B | X | |||
| SDMMC1_CMD | PIO_PA12B | X | |||
| – | |||||
| SDMMC1_CK | PIO_PA13B | ||||
| NAND Flash | HSMC | 1 | D16–D23 | PIO_PD6A-PIO_PD13A | – |
| NANDOE | PIO_PD0A | – | |||
| NANDWE | PIO_PD1A | – | |||
| NAND ALE | PIO_PD2A | – | |||
| NAND CLE | PIO_PD3A | – | |||
| NANDCS3 | PIO_PD4A | – | |||
| NAND WAIT | PIO_PD5A | – | |||
| 2 | NANDOE | PIO_PD0A | – | ||
| NANDWE | PIO_PD1A | – | |||
| A21-A22 | PIO_PD2A-PIO_PD3A | – | |||
| NANDCS3 | PIO_PD4A | – | |||
| NAND WAIT | PIO_PD5A | – | |||
| D0-D7 | – | – | |||
| A20 | PIO_PD15B | – | |||
| A23-A25 | PIO_PD16B-PIO_PD18B | – | |||
| NANDCS2 | PIO_PD19B | – | |||
| NANDCS4 -NANDCS5 | PIO_PD20B-PIO_PD21B | – | |||
| SPI Flash | FLEXCOM0_SPI | 1 | MOSI | PIO_PA0A | – |
| MISO | PIO_PA1A | X | |||
| NPCS0 | PIO_PA3A | – | |||
| SPCK | PIO_PA4A | – | |||
| 2 | MOSI | PIO_PA0A | – | ||
| MISO | PIO_PA1A | X | |||
| NPCS1 | PIO_PA2A | – | |||
| SPCK | PIO_PA4A | – | |||
| FLEXCOM1_SPI | 1 | MOSI | PIO_PA5A | – | |
| MISO | PIO_PA6A | X | |||
| NPCS0 | PIO_PC28C | – | |||
| SPCK | PIO_PC29C | – | |||
| 2 | MOSI | PIO_PA5A | – | ||
| MISO | PIO_PA6A | X | |||
| NPCS1 | PIO_PC27C | – | |||
| SPCK | PIO_PC29C | – | |||
| FLEXCOM2_SPI | 1 | MOSI | PIO_PA7A | – | |
| MISO | PIO_PA8A | X | |||
| SPCK | PIO_PB1B | – | |||
| NPCS0 | PIO_PB2B | – | |||
| 2 | MOSI | PIO_PA7A | – | ||
| MISO | PIO_PA8A | X | |||
| SPCK | PIO_PB2B | – | |||
| NPCS1 | PIO_PB0B | – | |||
| FLEXCOM3_SPI | 1 | MOSI | PIO_PC22B | – | |
| MISO | PIO_PC23B | X | |||
| NPCS0 | PIO_PC25B | – | |||
| SPCK | PIO_PC26B | X | |||
| 2 | MOSI | PIO_PC22B | – | ||
| MISO | PIO_PC23B | X | |||
| NPCS1 | PIO_PC24B | – | |||
| SPCK | PIO_PC26B | – | |||
| SPI Flash | FLEXCOM4_SPI | 1 | MISO | PIO_PA11A | X |
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS0 | PIO_PA14A | – | |||
| 2 | MISO | PIO_PA11A | X | ||
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS1 | PIO_PA0C | – | |||
| 3 | MISO | PIO_PA11A | X | ||
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS1 | PIO_PA7B | – | |||
| 4 | MISO | PIO_PA11A | X | ||
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS2 | PIO_PA1B | – | |||
| 5 | MISO | PIO_PA11A | X | ||
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS2 | PIO_PA8C | – | |||
| 6 | MISO | PIO_PA11A | X | ||
| MOSI | PIO_PA12A | – | |||
| SPCK | PIO_PA13A | – | |||
| NPCS3 | PIO_PB3B | – | |||
| SPI Flash | FLEXCOM5_SPI | 1 | NPCS0 | PIO_PA8B | – |
| MISO | PIO_PA21B | X | |||
| MOSI | PIO_PA22B | – | |||
| SPCK | PIO_PA23B | – | |||
| 2 | NPCS1 | PIO_PA0B | – | ||
| MISO | PIO_PA21B | X | |||
| MOSI | PIO_PA22B | – | |||
| SPCK | PIO_PA23B | – | |||
| 3 | MISO | PIO_PA21B | X | ||
| MOSI | PIO_PA22B | – | |||
| SPCK | PIO_PA23B | – | |||
| NPCS1 | PIO_PA7C | – | |||
| 4 | MISO | PIO_PA21B | X | ||
| MOSI | PIO_PA22B | – | |||
| SPCK | PIO_PA23B | – | |||
| NPCS2 | PIO_PA31B | – | |||
| 5 | MISO | PIO_PA21B | – | ||
| MOSI | PIO_PA22B | X | |||
| SPCK | PIO_PA23B | – | |||
| NPCS3 | PIO_PA30B | – | |||
| QSPI Flash | QSPI_0 | 1 | QSCK | PIO_PB19A | – |
| QCS | PIO_PB20A | – | |||
| QIO0 | PIO_PB21A | X | |||
| QIO1 | PIO_PB22A | X | |||
| QIO2 | PIO_PB23A | X | |||
| QIO3 | PIO_PB24A | X | |||
| Console and SAM-BA Monitor | DBGU | 1 | DTXD | PIO_PA10A | – |
| DRXD | PIO_PA9A | – | |||
| FLEXCOM0_ UART | 1 | DTXD | PIO_PA0A | – | |
| DRXD | PIO_PA1A | – | |||
| FLEXCOM1_UART | 1 | DTXD | PIO_PA5A | – | |
| DRXD | PIO_PA6A | – | |||
| FLEXCOM2_UART | 1 | DTXD | PIO_PA7A | – | |
| DRXD | PIO_PA8A | – | |||
| FLEXCOM3_UART | 1 | DTXD | PIO_PC22B | – | |
| DRXD | PIO_PC23B | – | |||
| FLEXCOM4_UART | 1 | DTXD | PIO_PA12A | – | |
| DRXD | PIO_PA11A | – | |||
| FLEXCOM5_UART | 1 | DTXD | PIO_PA22B | – | |
| DRXD | PIO_PA21B | – | |||
| FLEXCOM6_UART | 1 | DTXD | PIO_PA30A | – | |
| DRXD | PIO_PA31A | – | |||
| FLEXCOM7_UART | 1 | DTXD | PIO_PC0C | – | |
| DRXD | PIO_PC1C | – | |||
| FLEXCOM8_UART | 1 | DTXD | PIO_PB4B | – | |
| DRXD | PIO_PB5B | – | |||
| FLEXCOM9_UART | 1 | DTXD | PIO_PC8C | – | |
| DRXD | PIO_PC9C | – | |||
| FLEXCOM10_UART | 1 | DTXD | PIO_PC16C | – | |
| DRXD | PIO_PC17C | – | |||
| FLEXCOM11_UART | 1 | DTXD | PIO_PB19C | – | |
| DRXD | PIO_PB20C | – | |||
| FLEXCOM12_UART | 1 | DTXD | PIO_PB21C | – | |
| DRXD | PIO_PB22C | – |