10.1.6.1 DDR-SDRAM Controller (MPDDRC) and SDRAM Controller (SDRAMC)

The MPDDRC and SDRAMC are respectively compliant with the following JEDEC standards:

DDR2-SDRAM: JESD79-2F with operating frequencies up to 200 MHz
LPDDR-SDRAM: JESD209B with operating frequencies up to 200 MHz
SDR-SDRAM: PC100 and PC133 with frequencies up to 200 MHz
LPSDR-SDRAM : PC100 and PC133 with low-power extensions and frequencies up to 166 MHz

The physical interface (PCB layout) between the processor and its memory has a major impact on signal integrity. Microchip provides IBIS models of the SAM9X60 device and strongly recommends to verify this processor-memory interface on a PCB simulation tool. For design guidance, refer to the application note “SAM9X60 Hardware Design Considerations” (AN3311), available on www.microchip.com.

The following table gives the recommended settings on the MPDDRC_RD_DATA_PATH.SHIFT_SAMPLING or SDRAMC_MDR.SHIFT_SAMPLING field depending on the memory type and on its operating frequency.

Table 10-21. SHIFT_SAMPLING Settings
SDRAM Type	SDRAM Clock Frequency	SHIFT_SAMPLING
DDR2-SDRAM	125 MHz ≤ f_{SDRAM_CLK} ≤ 200 MHz	2
LPDDR-SDRAM	f_{SDRAM_CLK} ≤ 200 MHz	2
SDR-SDRAM	f_{SDRAM_CLK} ≤ 200 MHz	3
LPSDR-SDRAM	f_{SDRAM_CLK} ≤ 166 MHz	3