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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Product Pages
SAM9X60
  1. Home
  2. 3 Memories
  3. 3.1 Overview
  4. 3.1.1 Embedded Memories
  5. 3.1.1.3 Boot Strategies

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
    • 3.1 Overview
      • 3.1.1 Embedded Memories
        • 3.1.1.1 Internal SRAM
        • 3.1.1.2 Internal ROM
        • 3.1.1.3 Boot Strategies
      • 3.1.2 External Memory
      • 3.1.3 Product Dependencies
      • 3.1.4 Special Functions in SFR
    • 3.2 External Bus Interface (EBI)
    • 3.3 Static Memory Controller (SMC)
    • 3.4 Programmable Multibit Error Correction Code Controller (PMECC)
    • 3.5 Programmable Multibit ECC Error Location Controller (PMERRLOC)
    • 3.6 DDR-SDRAM Controller (MPDDRC)
    • 3.7 SDRAM Controller (SDRAMC)
    • 3.8 OTP Memory Controller (OTPC)
  • 4 System Controller
  • 5 Image Subsystem
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
  • 8 Connectivity Subsystem
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

3.1.1.3 Boot Strategies

For standard boot strategies, refer to Standard Boot Strategy.

For secure boot strategies, refer to Secure Boot Strategy.

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