3.6.6.2 DDR-SDRAM Address Mapping for Low-cost Memories

Table 3-32. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 512 Columns, 2 Banks, 16 Bits
CPU Address Line
27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						Bk	Row[10:0]											Column[8:0]									M0

Table 3-33. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 512 Columns, 2 Banks, 16 Bits
CPU Address Line
27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						Row[10:0]											Bk	Column[8:0]									M0

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.