3.1.6 External Clock

A clarification has been made to Table 8-15 Start-Up Times for the External Clock Selection, where 14 CK in the column Additional Delay from Reset (V_CC = 5.0V) has been replaced by 19 CK. Functional changes are shown in bold.

Table 8-15. Start-Up Times for the External Clock Selection


Power Conditions	Start-Up Time from Power-Down and Power-Save	Additional Delay from Reset (V_CC = 5.0V)	SUT[1:0]
BOD enabled	6 CK	19 CK⁽¹⁾	00
Fast rising power	6 CK	19 CK + 4.1 ms	01
Slow rising power	6 CK	19 CK + 65 ms⁽²⁾	10
Reserved			11

Note:

If the RSTDISBL fuse is programmed, this start-up time will be increased to  19 CK + 4 ms to ensure the programming mode can be entered.
The device is shipped with this option selected.