25.3.4 Interrupts
Offset | Name | Vector Description | Conditions |
---|---|---|---|
0x00 | RXC | Receive Complete Interrupt |
|
0x02 | DRE | Data Register Empty Interrupt | The transmit buffer is empty/ready to receive new data (DREIE). |
0x04 | TXC | Transmit Complete Interrupt | The entire frame in the Transmit Shift register has been shifted out and there are no new data in the transmit buffer (TXCIE). |
When an interrupt condition occurs, the corresponding interrupt flag is set in the STATUS register (USART.STATUS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the Control A register (USART.CTRLA).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The interrupt request remains active until the interrupt flag is cleared. See the USART.STATUS register for details on how to clear interrupt flags.