34.5.8 ASI System Control A
| Name: | ASI_SYS_CTRLA |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UROWWRITE_FINAL | CLKREQ | ||||||||
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 1 – UROWWRITE_FINAL User Row Programming Done
This bit should be written through the UPDI when the user row data has been written to the RAM. Writing this bit will start the process of programming the user row data to the Flash.
If this bit is written before the User Row code is written to RAM by the UPDI, the CPU will progress without the written data.
This bit is only writable if the Userrow-write KEY is successfully decoded.
Bit 0 – CLKREQ Request System Clock
If this bit is written to '1', the ASI is requesting the system clock, independent of system Sleep modes. This makes it possible for the UPDI to access the ACC layer, also if the system is in Sleep mode.
Writing a zero to this bit will lower the clock request.
This bit will be reset when the UPDI is disabled.
This bit is set by default when the UPDI is enabled in any mode (Fuse, 12V).