23.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Enable-protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKSEL[1:0] | CNTPRES[1:0] | SYNCPRES[1:0] | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:5 – CLKSEL[1:0] Clock Select
The clock select bits select the clock source of the TCD clock.
| Value | Description |
|---|---|
| 0x0 | OSC20M |
| 0x1 | Reserved |
| 0x2 | External clock |
| 0x3 | System clock |
Bits 4:3 – CNTPRES[1:0] Counter Prescaler
The Counter Prescaler bits select the division factor of the TCD counter clock.
| Value | Description |
|---|---|
| 0x0 | Division factor 1 |
| 0x1 | Division factor 4 |
| 0x2 | Division factor 32 |
| 0x3 | Reserved |
Bits 2:1 – SYNCPRES[1:0] Synchronization Prescaler
The synchronization prescaler bits select the division factor of the TCD clock.
| Value | Description |
|---|---|
| 0x0 | Division factor 1 |
| 0x1 | Division factor 2 |
| 0x2 | Division factor 4 |
| 0x3 | Division factor 8 |
Bit 0 – ENABLE Enable
When this bit is written to, it will automatically be synchronized to the TCD clock domain.
This bit can be changed as long as synchronization of this bit is not ongoing, see Enable Ready bit (ENRDY) in Status register (TCDn.STATUS).
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | The TCD is disabled. |
| 1 | The TCD is enabled and running. |