25.5.2 Receiver Data Register High Byte
Reading the USARTn.RXDATAH register location will return the contents of the ninth DATA bit plus Status bits.
The receive buffer consists of a two-level FIFO. The FIFO and the corresponding flags in the high byte of USARTn.RXDATAH will change state whenever the receive buffer is accessed (read). If CHSIZE in USARTn.CTRLC is set to 9BIT Low byte first, read USARTn.RXDATAL before USARTn.RXDATAH. Otherwise, always read USARTn.RXDATAH before USARTn.RXDATAL in order to get the correct flags.
| Name: | RXDATAH |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXCIF | BUFOVF | FERR | PERR | DATA[8] | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty (i.e. does not contain any unread data). When the receiver is disabled, the receive buffer will be flushed and consequently, the RXCIF will become zero.
Bit 6 – BUFOVF Buffer Overflow
The BUFOVF flag indicates data loss due to a receiver buffer full condition. This flag is set if a Buffer Overflow condition is detected. A Buffer Overflow occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift register, and a new Start bit is detected. This flag is valid until the receive buffer (USARTn.RXDATAL) is read.
This flag is not used in Master SPI mode of operation.
Bit 2 – FERR Frame Error
The FERR flag indicates the state of the first Stop bit of the next readable frame stored in the receive buffer. The bit is set if the received character had a Frame Error (i.e. when the first Stop bit was zero and cleared when the Stop bit of the received data is '1'. This bit is valid until the receive buffer (USARTn.RXDATAL) is read. The FERR is not affected by the SBMODE bit in USARTn.CTRLC since the receiver ignores all, except for the first Stop bit.
This flag is not used in Master SPI mode of operation.
Bit 1 – PERR Parity Error
If parity checking is enabled and the next character in the receive buffer has a Parity Error this flag is set. If Parity Check is not enabled the PERR will always be read as zero. This bit is valid until the receive buffer (USARTn.RXDATAL) is read. For details on parity calculation refer to 25.3.2.2.1 Parity. If USART is set to LINAUTO mode, this bit will be a Parity Check of the protected identifier field and will be valid when DATA[8] in USARTn.RXDATAH reads low.
This flag is not used in Master SPI mode of operation.
Bit 0 – DATA[8] Receiver Data Register
When USART receiver is set to LINAUTO mode, this bit indicates if the received data is within the response space of a LIN frame. If the received data is the protected identifier field, this bit will be read as zero. Otherwise, the bit will be read as one. For Receiver mode other than LINAUTO mode, DATA[8] holds the ninth data bit in the received character when operating with serial frames with nine data bits.