21.5.6 Control Register E Set - Normal Mode
Each Status bit can be read out either by reading TCAn.CTRLESET or TCAn.CTRLECLR.
| Name: | CTRLESET |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD[1:0] | LUPD | DIR | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:2 – CMD[1:0] Command
These bits are used for software control of update, restart, and reset the timer/counter. The command bits are always read as zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No command |
| 0x1 | UPDATE | Force update |
| 0x2 | RESTART | Force restart |
| 0x3 | RESET | Force hard Reset (ignored if TC is enabled) |
Bit 1 – LUPD Lock Update
Locking the update ensures that all buffers are valid before an update is performed.
| Value | Description |
|---|---|
| 0 | The buffered registers are updated as soon as an UPDATE condition has occurred. |
| 1 | No update of the buffered registers is performed, even though an UPDATE condition has occurred. |
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but this bit can also be changed from software.
| Value | Description |
|---|---|
| 0 | The counter is counting up (incrementing) |
| 1 | The counter is counting down (decrementing) |