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28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
Product Pages
PIC18F27Q84 PIC18F47Q84 PIC18F57Q84
  1. Home
  2. 38 CAN FD - Controller Area Network, Flexible Data-Rate
  3. 38.5 Message Transmission

  • Introduction
  • PIC18-Q84 Family Types
  • Features
  • 1 Packages
  • 2 Pin Diagrams
  • 3 Pin Allocation Tables
  • 4 Guidelines for Getting Started with PIC18-Q84 Microcontrollers
  • 5 Register and Bit Naming Conventions
  • 6 Register Legend
  • 7 PIC18 CPU
  • 8 Device Configuration
  • 9 Memory Organization
  • 10 NVM - Nonvolatile Memory Module
  • 11 VIC - Vectored Interrupt Controller Module
  • 12 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
  • 13 CRC - Cyclic Redundancy Check Module with Memory Scanner
  • 14 Resets
  • 15 WWDT - Windowed Watchdog Timer
  • 16 DMA - Direct Memory Access
  • 17 Power-Saving Modes
  • 18 PMD - Peripheral Module Disable
  • 19 I/O Ports
  • 20 IOC - Interrupt-on-Change
  • 21 PPS - Peripheral Pin Select Module
  • 22 CLC - Configurable Logic Cell
  • 23 CLKREF - Reference Clock Output Module
  • 24 TMR0 - Timer0 Module
  • 25 TMR1 - Timer1 Module with Gate Control
  • 26 TMR2 - Timer2 Module
  • 27 SMT - Signal Measurement Timer
  • 28 UTMR - Universal Timer Module
  • 29 CCP - Capture/Compare/PWM Module
  • 30 Capture, Compare, and PWM Timers Selection
  • 31 PWM - Pulse-Width Modulator with Compare
  • 32 CWG - Complementary Waveform Generator Module
  • 33 NCO - Numerically Controlled Oscillator Module
  • 34 DSM - Data Signal Modulator Module
  • 35 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
  • 36 SPI - Serial Peripheral Interface Module
  • 37 I2C - Inter-Integrated Circuit Module
  • 38 CAN FD - Controller Area Network, Flexible Data-Rate
    • 38.1 Module Overview
    • 38.2 Modes of Operation
    • 38.3 Configuration
    • 38.4 CAN FD Message Frames
    • 38.5 Message Transmission
      • 38.5.1 Transmit Message Object
      • 38.5.2 Loading Messages into Transmit FIFO
      • 38.5.3 Loading Messages Into Transmit Queue
      • 38.5.4 Requesting Transmission of Message in Transmit FIFO
      • 38.5.5 Requesting Transmission of Message in Transmit Queue
      • 38.5.6 C1TXREQ Register
      • 38.5.7 Transmit Priority
      • 38.5.8 Transmit Bandwidth Sharing
      • 38.5.9 Retransmission Attempts
      • 38.5.10 Aborting Transmission
      • 38.5.11 Remote Transmit Request (RTR)
      • 38.5.12 Mismatch of DLC and Payload Size During Transmission
      • 38.5.13 Transmit State Diagram
      • 38.5.14 Resetting Transmit FIFO
      • 38.5.15 Resetting Transmit Queue
    • 38.6 Transmit Event FIFO (TEF)
    • 38.7 Message Filtering
    • 38.8 Message Reception
    • 38.9 FIFO Behavior
    • 38.10 Timestamping
    • 38.11 Interrupts
    • 38.12 Error Handling
    • 38.13 Register Definitions: CAN FD Control
    • 38.14 Register Summary - CAN FD
  • 39 JTAG Boundary Scan
  • 40 HLVD - High/Low-Voltage Detect
  • 41 FVR - Fixed Voltage Reference
  • 42 Temperature Indicator Module
  • 43 ADC - Analog-to-Digital Converter with Computation and Context Module
  • 44 DAC - Digital-to-Analog Converter Module - 8-Bit
  • 45 CMP - Comparator Module
  • 46 ZCD - Zero-Cross Detection Module
  • 47 Instruction Set Summary
  • 48 ICSP™ - In-Circuit Serial Programming™
  • 49 Register Summary
  • 50 Electrical Specifications
  • 51 DC and AC Characteristics Graphs and Tables
  • 52 Packaging Information
  • 53 Appendix A: Revision History
  • Microchip Information

38.5 Message Transmission

The application needs to configure the FIFO or TXQ before it can be used for transmission (see Transmit FIFO Configuration and Transmit Queue Configuration).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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