33.5.12 PGA Control


Bit	7	6	5	4	3	2	1	0
	GAIN[2:0]			PGABIASSEL[1:0]				PGAEN
Access	R/W	R/W	R/W	R/W	R/W			R/W
Reset	0	0	0	0	0			0

Bits 7:5 – GAIN[2:0] GAIN

This bit field controls the PGA gain setting.

Value	Name	Description
0x0	1X	1x gain
0x1	2X	2x gain
0x2	4X	4x gain
0x3	8X	8x gain
0x4	16X	16x gain
Other	-	Reserved

Bits 4:3 – PGABIASSEL[1:0] PGA Bias Select

This bit field controls the bias current supplied to the PGA.


Value	Name	Description
`0x0`	100PCT	100% BIAS current. Usable for f_{CLK_ADC} ≤ 6 MHz.
`0x1`	75PCT	75% BIAS current. Usable for f_{CLK_ADC} ≤ 4.5 MHz.
`0x2`	50PCT	50% BIAS current. Usable for f_{CLK_ADC} ≤ 3 MHz.
`0x3`	25PCT	25% BIAS current. Usable for f_{CLK_ADC} ≤ 1.5 MHz.

Bit 0 – PGAEN PGA Enable

This bit controls whether the PGA is enabled or not when selected by the VIA bit field in the Input Multiplexer (ADCn.MUXPOS or ADCn.MUXNEG) registers.

Note: If both PGAEN and Low Latency (LOWLAT) bit in the Control A (ADCn.CTRLA) register are ‘1’, the PGA will be continuously ON, even when not selected by the VIA bit field. This eliminates the initialization time if reconfiguring the ADC to use the PGA.

Value	Description
0	The PGA is disabled
1	The PGA is enabled

Name:	PGACTRL
Offset:	0x0B
Reset:	0x04
Property:	-