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AVR32EB14/20/28/32 Preliminary Data Sheet
Introduction
Family Overview
1 Memory Overview
2 Peripheral Overview
Security Concept
Features
1 Block Diagram
2 Pinout
2.1 14-Pin SOIC and TSSOP
2.2 20-Pin SSOP
2.3 28-Pin SPDIP and SSOP
2.4 28-Pin VQFN
2.5 32-Pin VQFN and TQFP
3 I/O Multiplexing and Considerations
3.1 I/O Multiplexing
4 Hardware Guidelines
4.1 General Guidelines
4.2 Connection for Power Supply
4.3 Connection for RESET
4.4 Connection for UPDI Programming
4.5 Connecting External Crystal Oscillators
4.6 Connection for External Voltage Reference
5 Power Domains
6 Conventions
6.1 Numerical Notation
6.2 Memory Size and Type
6.3 Frequency and Time
6.4 Registers and Bits
6.5 ADC Parameter Definitions
7 AVR® CPU
7.1 Features
7.2 Overview
7.3 Architecture
7.4 Functional Description
7.5 Register Summary
7.6 Register Description
8 Memories
8.1 Overview
8.2 Memory Map
8.3 In-System Reprogrammable Flash Program Memory
8.4 Program and Debug Interface Disable (PDID)
8.5 SRAM Data Memory
8.6 EEPROM Data Memory
8.7 SIGROW - Signature Row
8.8 USERROW - User Row
8.9 BOOTROW - Boot Row
8.10 FUSE - Configuration and User Fuses
8.11 LOCK - Memory Sections Access Protection
8.12 I/O Memory
9 GPR - General Purpose Registers
9.1 Register Summary
9.2 Register Description
10 Peripherals and Architecture
10.1 Peripheral Address Map
10.2 Interrupt Vector Mapping
10.3 SYSCFG - System Configuration
11 NVMCTRL - Nonvolatile Memory Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 CLKCTRL - Clock Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 SLPCTRL - Sleep Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 RSTCTRL - Reset Controller
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 CPUINT - CPU Interrupt Controller
15.1 Features
15.2 Overview
15.3 Functional Description
15.4 Register Summary
15.5 Register Description
16 EVSYS - Event System
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Register Summary
16.5 Register Description
17 PORTMUX - Port Multiplexer
17.1 Overview
17.2 Register Summary
17.3 Register Description
18 PORT - I/O Pin Configuration
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary - PORTx
18.5 Register Description - PORTx
18.6 Register Summary - VPORTx
18.7 Register Description - VPORTx
19 BOD - Brown-out Detector
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary
19.5 Register Description
20 VREF - Voltage Reference
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 WDT - Watchdog Timer
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary
21.5 Register Description
22 TCB - 16-Bit Timer/Counter Type B
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 TCE - 16-Bit Timer/Counter Type E
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary
23.5 Register Description
24 WEX - Waveform Extension for the 16-Bit Timer/Counter Type E
24.1 Feature Description
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 TCF - 24-bit Timer/Counter Type F
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 RTC - Real-Time Counter
26.1 Features
26.2 Overview
26.3 Clocks
26.4 RTC Functional Description
26.5 PIT Functional Description
26.6 Crystal Error Correction
26.7 Events
26.8 Interrupts
26.9 Sleep Mode Operation
26.10 Synchronization
26.11 Debug Operation
26.12 Register Summary
26.13 Register Description
27 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 SPI - Serial Peripheral Interface
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 TWI - Two-Wire Interface
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 CRCSCAN - Cyclic Redundancy Check Memory Scan
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 CCL - Configurable Custom Logic
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 AC - Analog Comparator
32.1 Features
32.2 Overview
32.3 Functional Description
32.4 Register Summary
32.5 Register Description
33 ADC - Analog-to-Digital Converter
33.1 Features
33.2 Overview
33.3 Functional Description
33.4 Register Summary
33.5 Register Description
34 UPDI - Unified Program and Debug Interface
34.1 Features
34.2 Overview
34.3 Functional Description
34.4 Register Summary
34.5 Register Description
35 Instruction Set Summary
36 Electrical Characteristics
36.1 Disclaimer
36.2 Absolute Maximum Ratings
36.3 Standard Operating Conditions
36.4 Supply Voltage
36.5 Power Consumption
36.6 Peripherals Power Consumption
36.7 I/O Pins
36.8 Memory Programming Specifications
36.9 Thermal Specifications
36.10 CLKCTRL
36.11 RSTCTRL and BOD
36.12 VREF
36.13 USART
36.14 SPI
36.15 TWI
36.16 ADC
36.17 AC
36.18 UPDI
37 Characteristics Graphs
38 Ordering Information
39 Packaging Information
39.1 Online Package Drawings
39.2 Package Marking Information
39.3 Package Drawings
40 Data Sheet Revision History
40.1 Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature