16.3.2.3 Event Generators

Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.

A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a sleep mode when the peripheral clock is not running.

Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.

Table 16-1. Properties of Generated Events
Event Type	Sync/Async	Description
Pulse	Sync	An event generated from CLK_PER that lasts one clock cycle
Pulse	Async	An event generated from a clock other than CLK_PER lasting one clock cycle
Level	Sync	An event generated from CLK_PER that lasts multiple clock cycles
Level	Async	An event generated without a clock (for example, a pin or a comparator), or an event generated from a clock other than CLK_PER that lasts multiple clock cycles

The properties of both the generated event and the intended event user must be considered in order to ensure reliable and predictable operation.

The table below shows the available event generators for this device family.

Table 16-2. Event Generators
Generator Name		Description	Event Type	Generating Clock Domain	Length of Event
Peripheral	Event	Description	Event Type	Generating Clock Domain	Length of Event
UPDI	SYNCH	SYNCH character	Async, Level	CLK_PDI	SYNCH character on PDI RX input synchronized to CLK_PDI
RTC	OVF	Counter Overflow	Async, Pulse	CLK_RTC	One CLK_RTC period
	CMP	Compare Match	Async, Pulse	CLK_RTC	One CLK_RTC period
	EVGEN0	Selectable prescaled RTC event	Async, Level	CLK_RTC	Prescaled RTC period
	EVGEN1	Selectable prescaled RTC event	Async, Level	CLK_RTC	Prescaled RTC period
CCL	LUTn	LUT output level	Async, Level	Asynchronous	Depends on CCL configuration
ACn	OUT	Comparator output level	Async, Level	Asynchronous	Given by AC output level
ADC0	RES	Result ready	Sync, Pulse	CLK_PER	One CLK_PER period
	SAMP	Sample ready
	WCMP	Window compare match
PORTx	EVGEN0	Pin level	Async, Level	Asynchronous	Given by pin level
PORTx	EVGEN1	Pin level	Async, Level	Asynchronous	Given by pin level
USARTn	XCK	Clock signal in SPI host mode and synchronous USART host mode	Sync, Level	TXCLK	Minimum two CLK_PER periods
SPI0	SCK	SPI host clock	Sync, Level	CLK_PER	Minimum two CLK_PER periods
TCE0	OVF	Overflow/ Low byte timer underflow	Sync, Pulse	CLK_PER	One CLK_PER period
	CMP0	Compare channel 0 match/Low byte timer compare channel 0 match	Sync, Pulse/Level		One CLK_PER period or WO
	CMP1	Compare channel 1 match/Low byte timer compare channel 1 match
	CMP2	Compare channel 2 match/Low byte timer compare channel 2 match
	CMP3	Compare channel 3 match/Low byte timer compare channel 3 match
TCBn	CAPT	CAPT interrupt flag set	Sync, Pulse/Level	CLK_PER	One CLK_PER period or WO
TCBn	OVF	Counter overflow	Sync, Pulse	CLK_PER	One CLK_PER period
TCF0	OVF	Counter overflow	Async, Pulse	CLK_TCF	One CLK_TCF period
	CMP0	Compare channel 0	Async, Pulse/Level		One CLK_TCF period or WO
	CMP1	Compare channel 1	Async, Pulse/Level		One CLK_TCF period or WO