UPDI One-Wire Interface for External
Programming and On-Chip-Debugging (OCD)
Enable programming by high-voltage or fuse
Uses the
RESET pin to enable the UPDI function, and one UPDI
pin of the device for programming
Asynchronous half-duplex UART
protocol towards the programmer
Programming:
Built-in error detection and error
signature generation
Override of response generation
for faster programming
Debugging:
Memory-mapped access to device
address space (NVM, RAM, I/O)
No limitation on the device clock
frequency
Unlimited number of user program
breakpoints
Two hardware breakpoints
Support for advanced OCD features
Run-time readout of the CPU
Program Counter (PC), Stack Pointer (SP) and Status Register (SREG) for code
profiling
Detection and signalization
of the Break/Stop condition in the CPU
Program flow control for
Run, Stop and Reset debug instructions
Nonintrusive run-time chip
monitoring without accessing the system registers
Interface for reading the result
of the CRC check of the Flash on a locked device
Programming and Debug Interface Disable (PDID) Security Functionality
UPDI access can be limited by
PDICFG and LOCK fuses
Bootloader still negotiating
firmware updates
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
