2 Our Approach
The main objective of this application note is to provide SAMA5D2 adopters with practical implementation guidelines and software settings, inferred from actual hardware and extensive tests performed on that hardware:
To ensure proper functionality of all SDRAM devices supported by the external memory controller (MPDDRC), numerous hardware and software considerations must be taken into account. While low-speed circuits have few physical constraints on the PCB, circuits featuring high-speed signals do have constraints that must be applied regarding trace length, width and clearance, PCB stacking, and length matching. These rules were applied when designing previously released development kits such as SAMA5D2-XULT and SAMA5D2-PTC-EK. In addition, a custom board has been designed and produced for the purpose of further testing to ensure proper compatibility of SAMA5D2 MPUs with all supported SDRAM devices from different manufacturers.
In addition to the boards, several pieces of testing software were developed. See the figure below.
The table below describes the testing cases.
| Test Case No. | Description | Purpose |
|---|---|---|
| 1 | Performs pin stuck at high/low test Writes sequential data patterns | Checks data integrity |
| 2 | Generates and writes random data | Checks data mismatch, unaligned access |
| 3 | Generates and transfers large data buffers | Checks data transfers in memory via DMA controller |
All SDRAM devices are tested at a clock frequency of 166 MHz (clock period is 6 ns).
Microchip performed such tests using a programmable climatic chamber.
During testing, all test results returned were logged for further analysis.