3 Hardware Aspects

Formerly released development kits containing SDRAM devices can be used as references when designing a new board. Layout examples for SDRAM implementation are provided.

Also, some general guidelines must be followed when routing such devices. Most SDRAM manufacturers provide application notes concerning high-speed signal routing, usually offering minimum and recommended constraints for trace width, clearance, length matching, etc. The distances are measured in mils, the usual metric for PCB design, where 1 mil = 0.0254 mm.

The SDRAM controller interface includes:

  • Four data byte lanes (see Note 1): DQS[3:0], DQSN[3:0], DQM[3:0], D[31:0]
  • ADDR/CMD/CTL signals: BA[2:0], A[13:0], RAS/CAS, CS, CKE, WE, RESETN
  • Clock signals: CK/CKn

Below is an exhaustive list of design guidelines for SDRAM signals, grouped by signal types (refer to Technical Note TN-46-14):

  • All SDRAM signals:
    • Trace width (see Note 2) for all signals should be 4 mils minimum (0.101 mm) and nominal width should be 6 mils (0.152 mm).
    • The reference power planes must have no splits across any high-speed signal.
    • The impedance of any single-ended signal trace should be 50 ±10% Ω.
    • The impedance of any differential signal trace should be 100 ±10% Ω.
  • Data lane signals recommendations:
    • Clearance between two adjacent data signals (includes D, DQS, DQM) should be 8 mils minimum and 12 mils nominal (see Note 2).
    • Signals belonging to the same data byte lane should be routed on the same layer.
    • Trace length difference between signals from the same data byte lane should not exceed 50 mils.
    • Different D byte lanes should be matched within 0.5 inch of each other.
    • DQS/DQSN signal pairs should be routed as differential signals with the length difference between traces not exceeding 20 mils.
    • The length difference between any data byte lane signal and CK/CKn should not exceed 500 mils.
  • Address/Control/Clock signals recommendations (see Note 2):
    • Clearance between command/control signals should be 6 mils minimum and 15 mils nominal.
    • Clearance between address signals should be 6 mils minimum and 12 mils nominal.
    • Clearance between address/control and data signals should be at least 20 mils.
    • Clearance between clock signals of the same differential pair should be 4 mils minimum and 6 mils nominal.
    • Clearance between the differential CK/CKn signal and any other signal should be 8 mils minimum and 12 mils nominal.
    • This type of signals should be routed on the same layer.
    • CK/CKn should be routed as differential signals with the length difference between traces not exceeding 20 mils.
    • The length difference between any address/control signal and CK/CKn should not exceed 400 mils.
      Note:
      1. A data byte lane is a group of SDRAM signals which ensures that byte-formatted data are properly transferred between the SDRAM device and controller. It features 8 data signals (D[7:0]), one data mask signal (DQM) and a pair of data strobe signals (DQS/DQSN). An 8-, 16- or 32-bit SDRAM device has one, two or four data byte lanes, respectively.
      2. The trace width and clearance values from these recommendations are chosen in order to match the desired impedance of each signal trace in relation with manufacturable PCB parameters, e.g. dielectric height. Consult the PCB manufacturer to accurately optimize these values.

Refer to the Micron technical note TN-46-14 “Hardware Tips for Point-to-Point System Design Introduction” for more details.