20.4.1 PMD Register Summary
Note: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0xBF | Reserved | |||||||||
| 0xC0 | PMD1 | 7:0 | ADCMD | ACMD | PLVDMD | LPAMD | MPAMD | BTMD | ZBMD | |
| 15:8 | ADCSARMD | |||||||||
| 23:16 | RTCCMD | |||||||||
| 31:24 | SQIMD |