13.14 Reference Clock Generator

The Reference Clock Generator provides the Generic Clocks (GCLK_<Periperhal>) for system peripherals via Peripheral Channels. There are a total of 24 Peripheral Channels with the mapping as shown in following table.

Table 13-1. Peripheral Clock Generation
Peripheral Clock	Pchannel Index
GCLK_EIC, GCLK_CCL	0
GCLK_FREQM_MSR	1
GCLK_FREQM_REF	2
GCLK_SERCOM0_CORE, GCLK_SERCOM1_CORE	3
GCLK_SERCOM2_CORE, GCLK_SERCOM3_CORE	4
GCLK_TC0	5
GCLK_TC1	6
GCLK_TC2, GCLK_TC3	7
GCLK_EVSYS_CH_0	8
GCLK_EVSYS_CH_1	9
GCLK_EVSYS_CH_2	10
GCLK_EVSYS_CH_3	11
GCLK_EVSYS_CH_4	12
GCLK_EVSYS_CH_5	13
GCLK_EVSYS_CH_6	14
GCLK_EVSYS_CH_7	15
GCLK_EVSYS_CH_8	16
GCLK_EVSYS_CH_9	17
GCLK_EVSYS_CH_10	18
GCLK_EVSYS_CH_11	19
GCLK_TCC0	20
GCLK_TCC1, GCLK_TCC2	21
GCLK_AC	22
GCLK_CM4_TRACE	23

The mapping for the source of the clocks for both the CLKGEN generator and Reference clock generator are shown in following table.

Table 13-2. CRU Clock Mapping
clock_in[x]	MCS/COSC Mapping	REFO/ROSEL Mapping	FSCM Clock Source	Clock to Switch to on a FSCM Fail
0 - FRC	0000	0000	—	X
1 - SPLL_CLK1	0001	0001	—	—
2 - POSC (16 MHz)	0010	0010	—	—
3- SOSC	0011	0011	—	—
4 - LPRC	0100	0100	X	—
5 - SPLL_CLK3 (RFPLL, 96 MHz)	—	0101	—	—
6 - PB1_CLK	—	0110	—	—
7 - SYS_CLK	—	0111	—	—
8 - REFI Pin	—	1000	—	—