22.6.5 Interrupts
The DMAC channels have the following interrupt sources:
- Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. See Data Transmission from Related Links.
- Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor has been fetched. See Error Handling from Related Links.
- Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. See Channel Suspend and Data Transmission from Related Links.
Each interrupt source has an Interrupt flag
associated with it. The Interrupt flag in the Channel Interrupt Flag Status and Clear
(CHINTFLAG) register is set when the Interrupt condition occurs. Each interrupt can be
individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set
register (CHINTENSET=1), and disabled by setting the corresponding bit in
the Channel Interrupt Enable Clear register (CHINTENCLR=1). The status of
enabled interrupts can be read from either INTENSET or INTENCLR.
An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear Interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. See Nested Vector Interrupt Controller (NVIC) from Related Links.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which Interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective Interrupt flags.