33.7.5 Serial Clock Phase and Polarity
Four combinations of polarity and phase are available for data transfers. Writing the Clock
Polarity bit in the QSPI Baud register (BAUD.CPOL) selects the polarity. The Clock Phase
bit in the BAUD register programs the clock phase (BAUD.CPHA). These two parameters
determine the edges of the clock signal on which data is driven and sampled. Each of the
two parameters has two possible states, resulting in four possible combinations
Note: The polarity/phase combinations are
incompatible. Thus, the interfaced client must use the
same parameter values to communicate.
| Clock Mode | BAUD.CPOL | BAUD.CPHA | Shift SCK Edge | Capture SCK Edge | SCK Inactive Level |
|---|---|---|---|---|---|
| 0 | 0 | 0 | Falling | Rising | Low |
| 1 | 0 | 1 | Rising | Falling | Low |
| 2 | 1 | 0 | Rising | Falling | High |
| 3 | 1 | 1 | Falling | Rising | High |
