33.8 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0							ENABLE	SWRST
		15:8
		23:16
		31:24								LASTXFER
0x04	CTRLB	7:0			CSMODE[1:0]		SMEMREG	WDRBT	LOOPEN	MODE
		15:8					DATALEN[3:0]
		23:16	DLYBCT[7:0]
		31:24	DLYCS[7:0]
0x08	BAUD	7:0							CPHA	CPOL
		15:8	BAUD[7:0]
		23:16	DLYBS[7:0]
		31:24
0x0C	RXDATA	7:0	DATA[7:0]
		15:8	DATA[15:8]
		23:16
		31:24
0x10	TXDATA	7:0	DATA[7:0]
		15:8	DATA[15:8]
		23:16
		31:24
0x14	INTENCLR	7:0					ERROR	TXC	DRE	RXC
		15:8						INSTREND		CSRISE
		23:16
		31:24
0x18	INTENSET	7:0					ERROR	TXC	DRE	RXC
		15:8						INSTREND		CSRISE
		23:16
		31:24
0x1C	INTFLAG	7:0					ERROR	TXC	DRE	RXC
		15:8						INSTREND		CSRISE
		23:16
		31:24
0x20	STATUS	7:0							ENABLE
		15:8							CSSTATUS
		23:16
		31:24
0x24 ... 0x2F	Reserved
0x30	INSTRADDR	7:0	ADDR[7:0]
		15:8	ADDR[15:8]
		23:16	ADDR[23:16]
		31:24	ADDR[31:24]
0x34	INSTRCTRL	7:0	INSTR[7:0]
		15:8
		23:16	OPTCODE[7:0]
		31:24
0x38	INSTRFRAME	7:0	DATAEN	OPTCODEEN	ADDREN	INSTREN		WIDTH[2:0]
		15:8	DDREN	CRMODE	TFRTYPE[1:0]			ADDRLEN	OPTCODELEN[1:0]
		23:16				DUMMYLEN[4:0]
		31:24
0x3C ... 0x3F	Reserved
0x40	SCRAMBCTRL	7:0							RANDOMDIS	ENABLE
		15:8
		23:16
		31:24
0x44	SCRAMBKEY	7:0	KEY[7:0]
		15:8	KEY[15:8]
		23:16	KEY[23:16]
		31:24	KEY[31:24]