18.4.7 Peripheral Clock Generator 2
The CFGPCLKGEN2 dictates the peripheral clock selection described in the Clock System chapter.
Note that the following bits EVSYSCX range from 1-8 which corresponds to channel 0 to 7. There is no Flash location for this register because the purpose of this register is to provide an application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN2 |
| Offset: | 0x70 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| C8D | EVSYSC8SEL[2:0] | C7D | EVSYSC7SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| C6D | EVSYSC6SEL[2:0] | C5D | EVSYSC5SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| C4D | EVSYSC4SEL[2:0] | C3D | EVSYSC3SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| C2D | EVSYSC2SEL[2:0] | C1D | EVSYSC1SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – C8D EVSYSC8 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 30:28 – EVSYSC8SEL[2:0] EVSYSC8 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 27 – C7D EVSYSC7 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 26:24 – EVSYSC7SEL[2:0] EVSYSC7 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 23 – C6D EVSYSC6 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 22:20 – EVSYSC6SEL[2:0] EVSYSC6 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 19 – C5D EVSYSC5 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – EVSYSC5SEL[2:0] EVSYSC5 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – C4D EVSYSC4 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – EVSYSC4SEL[2:0] EVSYSC4 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – C3D EVSYSC3 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – EVSYSC3SEL[2:0] EVSYSC3 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – C2D EVSYSC2 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – EVSYSC2SEL[2:0] EVSYSC2 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – C1D EVSYSC1 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – EVSYSC1SEL[2:0] EVSYSC1 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |