41.8.4 Synchronization Busy

This bit is cleared when the synchronization of the Compare/Capture Channel x register between the clock domains is complete.

This bit is set when the synchronization of the Compare/Capture Channel x register between clock domains is started.

The CCx bit is available only for existing Compare/Capture Channels. For details on the CC channels number, refer to each TCC feature list.

This bit is set when the synchronization of the CCx register between clock domains is started.

This bit is cleared when the synchronization of the PER register between the clock domains is complete.

This bit is set when the synchronization of the PER register between clock domains is started.

This bit is cleared when the synchronization of the WAVE register between the clock domains is complete.

This bit is set when the synchronization of the WAVE register between clock domains is started.

This bit is cleared when the synchronization of the PATTERN register between the clock domains is complete.

This bit is set when the synchronization of the PATTERN register between clock domains is started.

This bit is cleared when the synchronization of the COUNT register between the clock domains is complete.

This bit is set when the synchronization of the COUNT register between clock domains is started.

This bit is cleared when the synchronization of the STATUS register between the clock domains is complete.

This bit is set when the synchronization of the STATUS register between clock domains is started.

This bit is cleared when the synchronization of the CTRLB register between the clock domains is complete.

This bit is set when the synchronization of the CTRLB register between clock domains is started.

This bit is cleared when the synchronization of the ENABLE bit between the clock domains is complete.

This bit is set when the synchronization of the ENABLE bit between clock domains is started.

This bit is cleared when the synchronization of the SWRST bit between the clock domains is complete.