13.15.3.1 System Reset (SYSRST)

The internal System Reset (SYSRST) can be generated from multiple Reset sources, such as:

• Power-on Reset (POR)
• Brown-out Reset (BOR/ZPBOR)
• Master Clear Reset (MCLR)
• Watchdog Time-out Reset (WDTO)
• Deadman Timer Reset (DMTR)
• Software Reset (SWR)
• Configuration Mismatch Reset (CMR)
• Test Mode Entry and Exit Reset
• JTAG Reset

A system Reset is active at the first POR and asserted until device configuration settings are loaded and the oscillator clock sources become stable. The system Reset is then de-asserted, allowing the CPU to start fetching code after eight system clock cycles (SYSCLK). On any device Reset, no start-up time is required to transfer configuration values from the NVR memory into the configuration-holding registers. Once the device is active, the user may change the primary system clock source from FRC to SPLL by using the OSCCON register.