31.8.6 Interrupt Enable Set
| Name: | INTENSET |
| Offset: | 0x16 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | SSL | RXC | TXC | DRE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will set the Error Interrupt
Enable bit, which enables the Error interrupt.
| Value | Description |
|---|---|
| 0 | Error interrupt is disabled. |
| 1 | Error interrupt is enabled. |
Bit 3 – SSL Client Select Low Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will set the Client Select Low Interrupt Enable bit, which enables the Client Select Low interrupt.
| Value | Description |
|---|---|
| 0 | Client Select Low interrupt is disabled. |
| 1 | Client Select Low interrupt is enabled. |
Bit 2 – RXC Receive Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will set the Receive Complete
Interrupt Enable bit, which enables the Receive Complete interrupt.
| Value | Description |
|---|---|
| 0 | Receive Complete interrupt is disabled. |
| 1 | Receive Complete interrupt is enabled. |
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will set the Transmit Complete
Interrupt Enable bit, which enables the Transmit Complete interrupt.
| Value | Description |
|---|---|
| 0 | Transmit Complete interrupt is disabled. |
| 1 | Transmit Complete interrupt is enabled. |
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will set the Data Register Empty
Interrupt Enable bit, which enables the Data Register Empty interrupt.
| Value | Description |
|---|---|
| 0 | Data Register Empty interrupt is disabled. |
| 1 | Data Register Empty interrupt is enabled. |