65.5.2 Power Management

The system embeds three transceivers.

The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock (UPLLCK) is provided by the UTMI PLL.

In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI.

The High-speed transceiver returns a 30 MHz clock to the USB Host controller.

The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be generated by a PLL with a correct accuracy of +/-0.25% using the USBDIV field.

Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the bus USB signals (recovered 12 MHz domain) in Full-speed operations.

For High-speed operations, the user has to perform the following:

Enable UHPHS peripheral clock in the PMC.
Start the UPLL with a 480 MHz output frequency following the recommendation provided in section "USB Clock Controller" in chapter "Power Management Controller (PMC)".
Select UPLLCK as Input clock of OHCI part (USBS bit in PMC_USB register).
Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is selected.
Enable OHCI clocks with UHP bit in PMC_SCER.

For OHCI Full-speed operations only, the user can use the PLLA, and in this case has to perform the following:

Enable UHPHS peripheral clock in the PMC.
Select PLLACK as Input clock of OHCI part (USBS bit in PMC_USB register).
Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to be calculated according to the PLLACK value and USB Full-speed accuracy.
Enable the OHCI clocks with UHP bit in PMC_SCER.

Figure 65-3. UHP Clock Trees