55.4.4.1 GMAC I/Os

For RGMII operations, G0_TXCK must be configured with the internal pull-up resistor enabled to avoid a floating line when connecting an Ethernet PHY having a high input impedance.

The device’s MAC interface complies with the RGMII v1.3 specification that requires on the TX side a typical 2 ns data-to-clock time lapse at PCB level between the transmitting port (device) and the receiving port (Ethernet PHY). In practice, it is convenient to select Ethernet PHYs that can add this 2 ns time lapse on their TXC input. As an example, Microchip KSZ9131 features an internal DLL to delay the TXC line.