Programmable transfer delays between consecutive transfers,
between clock and data, between deactivation and activation of chip select
SPI Mode
Interface to serial peripherals such as ADCs and sensors
8-bit/16-bit programmable data length
Serial Memory Mode
Interface to serial memories operating in Single-bit SPI, Dual
SPI, Quad SPI and Octal SPI
Interface to serial memories operating in Single Data Rate or
Double Data Rate modes
Supports “Execute In Place” (XIP)— code execution by the system
directly from a serial memory
Flexible instruction register for compatibility with all serial Flash memories
Up to 32-bit address mode to support serial Flash memories
larger than 128 Mbits
Continuous Read mode (optimized transfer performance for
sequential read)
“On-the-fly” scrambling/unscrambling
Connection to DMA Channel
Capabilities Optimizes Data Transfers
One channel for the receiver, one channel for the
transmitter
Register Write Protection
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
