The following configuration values are valid for all listed bit names of this
register:
0: The corresponding source of interrupt is disabled.
1: The corresponding source of interrupt is enabled.
Name:
I2SMCC_IMRA
Offset:
0x18
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
RXROVF3
RXLOVF3
RXROVF2
RXLOVF2
RXROVF1
RXLOVF1
RXROVF0
RXLOVF0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RXRRDY3
RXLRDY3
RXRRDY2
RXLRDY2
RXRRDY1
RXLRDY1
RXRRDY0
RXLRDY0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TXRUNF3
TXLUNF3
TXRUNF2
TXLUNF2
TXRUNF1
TXLUNF1
TXRUNF0
TXLUNF0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TXRRDY3
TXLRDY3
TXRRDY2
TXLRDY2
TXRRDY1
TXLRDY1
TXRRDY0
TXLRDY0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x
(x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0
only) or TDM Channel 2x Overrun Interrupt Mask
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x
(x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0
only) or TDM Channel 2x Ready Interrupt Mask
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x
(x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x
(x=0 only) or TDM Channel 2x Underrun Interrupt Mask
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x
(x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x
(x=0 only) or TDM Channel 2x Ready Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
