11.4 DMA Controller Peripheral Connections
DMA Controller 0 manages transfers between peripherals and memory, and receives the triggers from the peripherals listed in the following table.
Instance Name | Channel T/R | Interface Number |
---|---|---|
FLEXCOM0 | Transmit | 0 |
FLEXCOM0 | Receive | 1 |
FLEXCOM1 | Transmit | 2 |
FLEXCOM1 | Receive | 3 |
FLEXCOM2 | Transmit | 4 |
FLEXCOM2 | Receive | 5 |
FLEXCOM3 | Transmit | 6 |
FLEXCOM3 | Receive | 7 |
FLEXCOM4 | Transmit | 8 |
FLEXCOM4 | Receive | 9 |
FLEXCOM5 | Transmit | 10 |
FLEXCOM5 | Receive | 11 |
FLEXCOM6 | Transmit | 12 |
FLEXCOM6 | Receive | 13 |
FLEXCOM7 | Transmit | 14 |
FLEXCOM7 | Receive | 15 |
FLEXCOM8 | Transmit | 16 |
FLEXCOM8 | Receive | 17 |
FLEXCOM9 | Transmit | 18 |
FLEXCOM9 | Receive | 19 |
FLEXCOM10 | Transmit | 20 |
FLEXCOM10 | Receive | 21 |
FLEXCOM11 | Transmit | 22 |
FLEXCOM11 | Receive | 23 |
FLEXCOM12 | Transmit | 24 |
FLEXCOM12 | Receive | 25 |
QSPI | Transmit | 26 |
QSPI | Receive | 27 |
DBGU | Transmit | 28 |
DBGU | Receive | 29 |
TDES | Receive | 30 |
TDES | Transmit | 31 |
AES | Transmit | 32 |
AES | Receive | 33 |
SHA | Transmit | 34 |
CLASSD | Transmit | 35 |
I2SMCC | Transmit | 36 |
I2SMCC | Receive | 37 |
SSC | Transmit | 38 |
SSC | Receive | 39 |
ADC | Receive | 40 |
TC0 | Receive | 41 |
TC1 | Receive | 42 |
TC1_CPA | Compare Counter A, Timer Channel 1 | 43 |
TC4_CPA | Compare Counter A, Timer Channel 4 | 44 |
TC1_CPB | Compare Counter B, Timer Channel 1 | 45 |
TC4_CPB | Compare Counter B Timer Channel 4 | 46 |
TC1_CPC | Compare Counter C, Timer Channel 1 | 47 |
TC4_CPC | Compare Counter C, Timer Channel 4 | 48 |
TC1_ETRG | External Event trigger, timer channel 1 for TC1_ETRG | 49 |
TC4_ETRG | External Event trigger, timer channel 1 for TC4_ETRG | 50 |