29.5 USB Clock Controller

The user can select the PLLA or the UPLL output as the USB source clock by writing PMC_USB.USBS. If using the USB, the user must program the PLL to generate an appropriate frequency depending on PMC_USB.USBDIV.

When the PLL output is stable, i.e., the LOCK bit is set, the USB device and host clocks can be enabled by setting the UHP bits in the System Clock Enable register (PMC_SCER). To save power on this peripheral when it is not used, the user can set the UHP bits in the System Clock Disable register (PMC_SCDR). The UHP bits in the System Clock Status register (PMC_SCSR) gives the activity of this clock. The USB device and host ports requires both the 48 MHz signal and the peripheral clock. The USB peripheral clock may be controlled by means of the Peripheral Clock Controller.