25.1 Description

The Debug Unit (DBGU) provides a single entry point from the processor for access to all the debug capabilities of the product.

The DBGU features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions.

Moreover, the association with a DMA controller permits packet handling for these tasks with processor time reduced to a minimum.

The DBGU also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the Arm processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the Arm processor, making possible the handling of the DCC under interrupt control.

Chip identifier registers permit recognition of the device and its revision. These registers indicate the sizes and types of the on-chip memories, as well as the set of embedded peripherals.

A Force NTRST capability enables the software to decide whether to prevent access to the system via the In-circuit Emulator (ICE). This disables system access through the processor’s ICE, thus protecting the code stored in ROM by asserting the NTRST line of the processor’s ICE.