17.1 Description

The System Controller embeds 256 bits of General Purpose Backup registers organized as 8 32-bit registers.

It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 if a tamper event is detected on WKUP1 to WKUP8 pins. These pins are internally routed through the VDDCORE area, thus tamper events can be generated only when the VDDCORE is powered. These pins are also used for fast wake-up in Power Management Controller (PMC). Thus, if some WKUP pins are not enabled for fast wake-up in PMC, they can be enabled for tamper event detection. The immediate clear of the GPBR is enabled if RSTC_MR.ENGCLR=1.

The immediate clear on tamper detection can be extended to all General Purpose Backup registers by writing to ‘1’ GPBR_FCLR.FCLR.

If an event has been detected on WKUP pins enabled for event detection in RTC, it is not possible to write to the General Purpose Backup registers (SYS_GPBRx) while the event has not been cleared.

SYS_GPBR0 to SYS_GPBR7 can be individually (each 32-bit part-select) read- and write-protected by configuring GPBR_MR. This register is write-once, which means that once it has been configured, the read or write protection is available until the loss of VDDBU.